1. Field of the Invention
The present disclosure relates to methods of inline monitoring of transistor-to-transistor critical dimensions (CDs) and test structures, and, more particularly, to a method for estimating the risk of defects of gate electrodes formed in at least one active region.
2. Description of the Related Art
As the semiconductor industry continues pushing the boundaries of Moore's Law, there is a constant drive to scale down the critical dimensions (CDs) of circuit elements of an integrated circuit (IC) in order to increase the functionality of ICs within the smallest footprints. A critical issue that has to be taken into account at advanced scaling is how close rows of arrays of transistors can be stacked upon one another (or with regard to the wafer in two dimensions). This is important because the source and drain of a transistor device are to be completely separated by the gate. In fully-depleted silicon-on-insulator (FDSOI), for example, it is an issue that epitaxially grown raised source/drain regions may be overgrown around the ends of a gate structure, possibly leading to source/drain regions that are not completely separated. Another requirement concerns sufficient spacing between two adjacent gate structures and sufficient overlay between gate structures and active regions. These requirements induce constraints on a closest separation between adjacent transistors by the tip-to-tip (T2T) distance between two adjacent gate structures.
FIG. 1 schematically illustrates, in a top view, a common prior art SRAM memory cell structure 100 comprising two columns of gate structures 10, 20, 30 and 40, the gate structures 10 and 30 being separated along a length direction by a distance d2, while the gate structures 20 and 40 are oriented in parallel to the gate structures 10 and 30, the gate structures 20 and 40 being separated by a distance d1. Usually, the gate structures 10 and 30 are formed as a single gate structure which is subsequently cut, forming the separated gate structures 10, 30, wherein the cut has the width d2. Similarly, the gate structures 20 and 40 are usually formed as a single gate structure which is subsequently cut, the cut having the width d1.
The cell structure 100 comprises a plurality of active regions 50, 60, 70 and 80 formed in an upper surface region of a semiconductor substrate and being electrically isolated from each other by insulating structures provided in the upper surface of the semiconductor substrate. As illustrated in FIG. 1, the gate structures 10 and 20 overlay the active region 50, wherein the gate structure 20 extends over the active region 60. Similarly, the gate structure 30 overlays the active regions 70 and 80, while the gate structure 40 overlays the active region 80. Upon appropriately contacting the active regions 50 to 80 and the gate structures 10 to 40, transistor device structures PG1, PG2, PU1, PD1 and PD2, PU2 may be connected to implement a six transistor (6T) memory cell, where two cross coupled inverters PU1, PD1 and PU2, PD2 are selectively accessible via pass through transistors PG1 and PG2.
The above described cell structure 100 is conventionally used to push the boundaries of the capability of a semiconductor manufacturing facility by aggressively scaling critical structures and CDs, such as the spacings d1 and d2 in FIG. 1. This allows for the increasing of the dimensions of the active areas 60 and 70 which improve performance and within wafer and die variation.
For example, in case of a poor overlay of the gate structure 10 and the active region 50, as indicated by a broken line in FIG. 1, the broken line indicating an end of the gate structure 10, a bridging may occur when epitaxially growing raised source/drain regions (not illustrated), the epitaxially growing material growing around the end of the gate structure 10 as indicated by an arrow A1 in FIG. 1. It is not difficult to see that the performance of the cell structure 100 depends on the spacings/cuts d1 and d2, because an unclear bridging between either of the gate structures 10, 30 (see arrow A1 in FIG. 1) and 20, 40 may severely impact the performance of the cell structure 100 and may possibly lead to undesired electric connections between neighboring gate structures.
Conventionally, T2T bridging may be detected during the SORT process when fabricating semiconductor devices. However, as SORT takes place at an advanced stage during processing, there are high costs associated with manufacturing wafers which won't yield after the gate all the way down to SORT.